The present invention relates to a decoding/encoding method for booting from a NAND Flash and a system thereof, and more particularly, to a decoding method and a system thereof for reading data which are previously written into the NAND Flash as duplicates of NAND booting information, and performing a voting scheme on the read data, for obtaining the NAND booting information, and thereof, an encoding method corresponding the same.
NAND Flash memory has many advantages such as high throughput, fast erasing time and the cost per Byte is much lower than NOR architecture-based Flash memories, and therefore is becoming an ideal solution for Personal Digital Assistant (PDA) and mobile phone platforms that require a large storage capacity for Operating System (OS) images and multimedia objects such as MP3 files. NAND Flash memory is a non-XIP (Execution in Place) memory, and therefore has to shadow codes to an XIP memory (e.g. a RAM) before booting from NAND Flash memory.
The NAND Flash array is grouped into a series of blocks, which are the smallest erasable units in a NAND Flash device. For example, a 2 Gb NAND Flash device is organized as 2,048 blocks, with 64 pages per block. Each page is 2,112 bytes, consisting of a 2,048-byte data area and a 64-byte spare area. The spare area is typically used for error correction code (ECC) for ensuring data integrity, wear-leveling and other software overhead functions. Please refer to FIG. 1, which is a schematic diagram of two conventional implementations for storing data and spare information in the same page according to the prior art. The FIG. 1(a) shows a first implementation of a 2,112-byte page containing four of these 528-byte elements, each involving a data area of 512 bytes plus the 16-byte spare area directly adjacent to it. The FIG. 1(b) shows a second implementation of storing the data and spare information separately. The four 512 byte data area are stored first, and their corresponding 16-byte spare area follow, in order, at the end of the page.
In addition, the current NAND Flash manufacturing includes a traditional single-level cell (SLC) technology, which can store only 1 bit of data per cell, and a multi-level cell (MLC) technology, which can store at least 2 bits of data per cell. Compared with SLC, MLC technology offers obvious density advantages but lacks the speed and reliability. An SLC NAND Flash uses simple Hamming code to correct a single bit error. However, from SLC to MLC NAND Flash, the ECC bit number is getting large, which increases the complexity of booting from NAND Flash.
When the system does not know what type the NAND Flash is, the system will first read the NAND Flash according to a setting of NAND booting information such as page size, address cycle, bus interface, ECC bit number, etc., from a booting page of a block 0 of the NAND Flash. If the used setting is incorrect and the ECC check is unsuccessful, the system will keep trying another setting of NAND booting information until successfully booting from the NAND Flash. For a NAND Flash with a page size equal to 4 KB, the iterations of its ECC bit number include 4, 6, 8, 10 and 12 bits. That is, the system may have to try 5 times at most for successfully booting from the NAND flash, not including trying another settings such as page size or address cycle.
On the other hand, in the booting page, NAND booting information occupies about 50 bytes. Please refer to FIG. 1 again, if the NAND Flash uses the first implementation as shown in FIG. 1(a), the system can only check the corresponding parity in the spare area after reading a data area of 512 bytes. Or, if the NAND Flash uses the second implementation as shown in FIG. 1(b), the system can only check the corresponding parity in the spare area after reading four data area of 512 bytes, which takes long time.
From the above, in the conventional booting method, the system may have to try a great deal of setting of NAND booting information to find out a suitable one. In addition, even if the NAND booting information only occupies a small part of the data area, the system still has to read the whole data area and the spare area and then can perform ECC check.